1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit comprising an interface circuit for receiving and sending data from and to an external device connected to an outside of the semiconductor integrated circuit and a bus for transmitting the data from the interface circuit into the semiconductor integrated circuit, a semiconductor integrated circuit comprising a phase-locked loop (hereinafter referred to as a PLL circuit) for synchronizing an internal clock with an external clock at a high speed, and a semiconductor integrated circuit comprising a DRAM which is small-sized and can easily be tested.
2. Description of the Background Art
In a semiconductor integrated circuit, generally, one chip has a plurality of functions. In other words, a plurality of internal devices having different functions are integrated into the same chip so that the semiconductor integrated circuit is formed. FIG. 15 is a block diagram showing a structure of a semiconductor integrated circuit which is a so-called one-chip microcomputer. The one-chip microcomputer is also formed with a plurality of internal devices provided on one chip 1. On the chip 1 is provided a CPU 2 which includes a control circuit for interpreting and executing instructions and serves to perform arithmetic operation. Data such as instructions sent to the CPU 2 are given from internal and external devices provided on the inside and outside of the semiconductor integrated circuit, respectively. The external device is connected to an input-output pin 3. An interface circuit 4 acting as one of the internal devices is connected to the input-output pin 3. The interface circuit 4 serves to electrically and functionally match data transfer between the external device connected to the input-output pin 3 and the internal device of the semiconductor integrated circuit. More specifically, the interface circuit 4 controls data transfer on a boundary between the inside and outside of the semiconductor integrated circuit.
In order for the CPU 2 to execute instructions, the semiconductor integrated circuit should fetch data necessary for the CPU 2. A processing speed of the CPU 2 is limited. Therefore, data generated in the semiconductor integrated circuit and data given from the outside should be held by any internal device until the CPU 2 starts a processing. In order to efficiently transmit data from the internal device such as the CPU 2 to the external device, it is also necessary to hold the data temporarily. In general, a storage is provided in the semiconductor integrated circuit in order to hold data to be processed by the CPU 2 or data waiting to be processed by the CPU 2 and output to the outside. Examples of the storage provided in the semiconductor integrated circuit include a SRAM 5 for sending and receiving data at a maximum speed together with the CPU 2, a DRAM 6 acting as a main memory for storing large scale data required by the CPU 2 and for holding and storing image data and the like when performing an image processing, and a NVRAM 7 for storing a basic program and data and for storing individual programs necessary for application.
The above-mentioned internal devices include the storage such as the SRAM 5 and the CPU 2 in addition to the interface circuit 4. In thecase where plural kinds of internal devices other than the interface circuit 4 are provided, the semiconductor integrated circuit can employ an indirect control method in which two or more channels such as a channel for transferring data between the external device and the CPU 2 and a channel for transferring data between the external device and the storage are provided and the interface circuit 4 is caused to switch channels. Furthermore, the semiconductor integrated circuit can also employ a direct control method for directly inputting data from the external device to the CPU 2 and transferring the same data from the CPU 2 to the storage. In the indirect control method, a selector channel and a multiplex channel are used. The selector channel serves to transfer data at a time without breaking a physical connecting relationship between the channel and the interface circuit 4 until data transfer is completed. The multiplex channel serves to transfer data while switching the physical connecting relationship between the channel and the interface circuit 4 on a unit.
Referring to a multi-channel, the interface circuit 4 switches the channels. Therefore, the interface circuit 4 requires information for switching the channels.
In a multi-channel switching method according to the prior art, channels are switched every byte of data or are switched for each block of data by causing the data to have information about channel selection.
Some kinds of data are transmitted. Data which can immediately be executed by the CPU 2 are directly sent to the CPU 2. Data which should be rewritten to a main memory or stored once are transmitted to a storage side such as the DRAM 6. As a matter of course, some data should be transmitted to the CPU 2 and the storage at the same time. Some of the data transmitted to the DRAM 6 are used for a cache. Such data are stored in the SRAM 5 simultaneously.
The data to be processed by the CPU 2 and output from the CPU 2 include data to be exactly output to an external device in addition to data to be transferred to the SRAM 5 and the DRAM 6. In such a case, the prior art can also employ a method for causing the DRAM 6 to store all the data once, connecting the interface circuit 4 to the DRAM 6 by a multiplexer (not shown) and sending only data to be output from the DRAM 6 to the external device. A PLL circuit 8 which is also used in the semiconductor integrated circuit shown in FIG. 15 will be described below. The PLL circuit 8 is provided to synchronize an internal clock used in the semiconductor integrated circuit with an external clock sent from the outside of the semiconductor integrated circuit. Also in a system chip, the PLL circuit is used. Referring to the system chip, a clock is always set to a power down mode, a refresh mode or the like. Also in such a case, it is important to realize high-speed synchronization in order to increase a speed of operation of the semiconductor integrated circuit performed in response to the internal clock. The internal clock should be synchronized with the external clock to perform communication between the external device and the semiconductor integrated circuit.
As shown in FIG. 17, the PLL circuit according to the prior art includes a frequency phase comparator 30 for detecting differences in frequencies and phases, a charge pump 31 for causing a current to flow into or out for a period of time corresponding to a result of the detection performed by the frequency phase comparator 30, a loop filter 32 for eliminating high-frequency components and noises from an output of the charge pump 31 to obtain a DC voltage, and a ring oscillator 33 for generating an internal clock having a frequency corresponding to an output of the loop filter 32. In the PLL circuit according to the prior art, one frequency phase comparator performs two processes, that is, a frequency leading-in process for causing frequencies to approximate to each other in order to synchronize the internal clock with the external clock, and a phase synchronizing process for completing phase synchronization.
The semiconductor integrated circuit according to the prior art has the above-mentioned structure. Therefore, input data always arrives at a predetermined destination, and data transfer is terminated while the data cannot be accepted at the destination until the data can be accepted at the same destination. For this reason, it takes a lot of time to transfer the data As shown in FIG. 15, for example, data having destination information is sent from the external device to the interface circuit 4 through the input-output pin 3. If the CPU 2 indicates the destination information of the data, the interface circuit 4 connects the CPU 2 and the channel to transmit the data through the connected channel. If the CPU 2 is in a busy state of instruction processing or the like and cannot receive the data, the channel cannot be disconnected before data transmission is completed. Consequently, the data cannot be transferred efficiently.
FIG. 16 is a block diagram showing a structure of an expand version of a semiconductor integrated circuit which is more suitable for processing mass data than in FIG. 15. In the semiconductor integrated circuit having the expand version shown in FIG. 16, a chip size is naturally increased and capacities of a SRAM 5 and a DRAM 6 are enlarged. Furthermore, a ROM 9 to store basic programs and the like is provided in addition to a NVRAM 7. In the semiconductor integrated circuit having the expand version which transmits mass data, a transfer efficiency should be prevented from being deteriorated. Such a problem is more serious than in an ordinary semiconductor integrated circuit.
In the case where data is transmitted from an internal device to an external device, all the data necessary for the external device should be transferred to the internal device in advance if a channel connected to the same external device is fixed. Consequently, a local link for connecting the internal devices becomes complicated.
In a semiconductor integrated circuit comprising the PLL circuit according to the prior art, one frequency phase comparator performs the two processes, that is, the frequency leading-in process for causing frequencies to approximate to each other in order to synchronize an internal clock with an external clock and the phase synchronizing process for completing phase synchronization. For this reason, if a frequency leading-in range is set wide, a setting time is increased.
In a semiconductor integrated circuit comprising the DRAM according to the prior art, the DRAM occupies great parts of the area and consumed power. If the DRAM is enlarged, the area and the consumed power of the semiconductor integrated circuit are increased.
A test for the DRAM often requires a technique for simultaneously writing the same data to a plurality of memory cells. In such a case, generally, it has been proposed that a word line is selected and then the data are sequentially written to the memory cells or that a register is provided on a side of a memory cell array and the data are written to the register and then are written to the memory cells in the memory cell array in a batch. In these cases, the DRAM has an overhead of a write cycle during batch write of data for performing the test in a test mode. Therefore, the semiconductor integrated circuit cannot operate at a high speed.
A first aspect of the present invention is directed to a semiconductor integrated circuit comprising an interface circuit, a multiplexer, first and second internal devices connected to the interface circuit through the multiplexer, respectively, and an internal bus for transmitting data between the first and second internal devices without using the multiplexer, wherein the first internal device outputs a processing signal to the interface circuit if the first internal circuit cannot accept data to be given to the first internal device, which data is input from an external device to the interface circuit, and the interface circuit controls the multiplexer on the basis of the processing signal and transfers, to the second internal device, the data to be given to the first internal device.
A second aspect of the present invention is directed to a semiconductor integrated circuit comprising an interface circuit, a multiplexer, first and second internal devices connected to the interface circuit through the multiplexer, respectively, and an internal bus for transmitting data between the first and second internal devices without using the multiplexer, wherein if there are data to be output from the first internal device to an external device through the interface circuit and data to be output from the second internal device to the external device through the interface circuit, the interface circuit controls the multiplexer according to information about data transfer given from the first internal device to the interface circuit and alternately outputs, to the external device, the data to be output from the first internal device and the data to be output from the second internal device.
A third aspect of the present invention is directed to a phase-locked loop circuit comprising first current output means for dividing a frequency of an external clock by that of an internal clock to calculate a quotient as an integer or an inverse number of the integer and for generating a first current proportional to the quotient, second current output means for generating a second current based on a phase difference between the external clock and the internal clock, and an oscillator for controlling a frequency on the basis of a sum of the first and second currents to generate the internal clock.
A fourth aspect of the present invention is directed to the phase-locked loop circuit according to the third aspect of the present invention, wherein the first current output means has a ring oscillator for shifting a phase of the internal clock synchronously with transition of the external clock, and a half cycle of an output of the ring oscillator is compared with that of the external clock to calculate the quotient.
A fifth aspect of the present invention is directed to the phase-locked loop circuit according to the fourth aspect of the present invention, wherein the second current output means has a bi-directional shift ring formed by connecting, like a ring, a plurality of bi-directional shift registers for performing shift in a direction corresponding to a sign of the phase difference at a shift speed according to the sum of the first and second currents, and the second current is increased or decreased on the basis of the direction of shift of the bi-directional shift ring.
A sixth aspect of the present invention is directed to a semiconductor integrated circuit comprising a word line, first and second bit lines which are paired with each other, at least one of which is selectively connected to a memory cell by the word line, third and fourth bit lines provided corresponding to the first and second bit lines respectively and paired with each other, a first transistor connected between the first and third bit lines in series and on-off controlled in response to a first signal sent to a control electrode, a second transistor connected between the second and fourth bit lines in series and on-off controlled in response to the first signal sent to a control electrode, first and second power lines capable of supplying a first voltage and a second voltage different from the first voltage, and of being cut off from a power supply to be brought into a floating state, a third power line for supplying a third voltage between the first and second voltages, switching means for connecting the third power line to the third and fourth bit lines in response to an equalize signal, a third transistor having a first current electrode connected to the first power line, a second current electrode connected to the third bit line, and a control electrode connected to the fourth bit line, a fourth transistor having a first current electrode connected to the first power line, a second current electrode connected to the fourth bit line, and a control electrode connected to the third bit line, a fifth transistor having a first current electrode connected to the second power line, a second current electrode connected to the third bit line, and a control electrode connected to the second bit line, and a sixth transistor having a first current electrode connected to the second power line, a second current electrode connected to the fourth bit line, and a control electrode connected to the first bit line.
A seventh aspect of the present invention is directed to a semiconductor integrated circuit comprising a first transistor having a first current electrode connected to storage nodes of memory cells, a second current electrode and a control electrode, the first transistor being conducted when the control electrode is at xe2x80x9cHighxe2x80x9d level and being non-conducted when the control electrode is at xe2x80x9cLowxe2x80x9d level, a word line connected to the control electrode of the first transistor, a first bit line connected to the second current electrode of the first transistor, a second bit line provided corresponding to the first bit line, a second transistor having a first current electrode connected to the first bit line, a second current electrode connected to the second bit line and a control electrode to which a first signal is sent, the second transistor being conducted when the first signal is at the xe2x80x9cHighxe2x80x9d level and being non-conducted when the first signal is at the xe2x80x9cLowxe2x80x9d level, a power line, a third transistor having a first current electrode connected to the power line, a second current electrode connected to the second bit line and a control electrode to which a second signal is sent, the third transistor being conducted when the second signal is at the xe2x80x9cHighxe2x80x9d level and being non-conducted when the second signal is at the xe2x80x9cLowxe2x80x9d level, and a negative voltage generating circuit capable of being selectively connected to the power line and supplying, to the power line, a negative voltage which can cause the power line to have a voltage lower than the xe2x80x9cLowxe2x80x9d level and make the first to third transistors conducted.
An eighth aspect of the present invention is directed to a semiconductor integrated circuit comprising a word line and a first bit line connected to each other through a memory cell, a second bit line provided corresponding to the first bit line, a first transistor having a first current electrode connected to the first bit line, a second current electrode connected to the second bit line, and a control electrode to which a first signal is sent, the first transistor being conducted when the first signal has a first potential and being non-conducted when the first signal has a second potential, a second transistor having a first current electrode connected to the second bit line, a second current electrode and a control electrode to which a second signal is sent, a power line connected to the second current electrode of the second transistor, and a potential generating circuit capable of being selectively connected to the power line and giving, to the power line, a potential different from an intermediate potential between the first and second potentials by a value greater than a threshold value of the second transistor when the second bit line is cut off from the first bit line by the first transistor so that the second bit line and the second signal have the intermediate potential.
According to the first aspect of the present invention, also in the case where the first internal device cannot accept data, the data can be transferred to the second internal device and then given from the second internal device to the first internal device by using the internal bus. Therefore, a data transfer efficiency between the external device and the semiconductor integrated circuit can be enhanced, and the data can be transmitted precisely.
According to the second aspect of the present invention, channels are switched by the multiplexer on the basis of information sent from the first internal device, and the data output from the first internal device and the data output from the second internal device are linked together to form a series of data. Consequently, data transfer between the first and second internal devices can be omitted. Thus, a data processing rate can be enhanced.
According to the third aspect of the present invention, a ratio of a frequency of the external dock to that of the internal clock can range from xc2xd to 2 by the first current. Therefore, a phase difference comparison for setting a second current can be performed quickly. Consequently, a speed at which the internal clock is lead into the external clock can be enhanced.
According to the fourth aspect of the present invention, it is easy to calculate the ratio of the frequency of the external clock to that of the internal clock as an integer or an inverse number of the integer.
According to the fifth aspect of the present invention, the bi-directional shift ring is used, a shift speed of which is controlled depending on a frequency. Therefore, high precision can be kept with a high frequency.
According to the sixth aspect of the present invention, the third and fourth transistors can be used as an amplifier of a sense amplifier and a latch. Therefore, a size of the semiconductor integrated circuit can be reduced correspondingly.
According to the seventh aspect of the present invention, batch writing is performed with a negative voltage. Consequently, an overhead of a write cycle is eliminated so that the semiconductor integrated circuit can operate at a higher speed.
According to the eighth aspect of the present invention, when the bit line has a precharge potential, data can be written to memory cells connected to an intended word line in a batch by causing the bit line to have a high or low potential.
In order to solve the above-mentioned problems, it is an object of the present invention to cause an interface circuit to have a function of changing a destination according to information given from an internal device to the interface circuit and to transfer data to other internal devices when an internal device to which the data should be transmitted cannot receive the data, thus reducing an average time in which the interface circuit is connected to a channel every unit quantity of the data.
It is another object of the present invention to synchronize an external clock with an internal clock even if a frequency is greatly changed and to reduce a time for the synchronization, thus increasing an operating speed of a semiconductor integrated circuit.
It is yet another object of the present invention to reduce a size of the semiconductor integrated circuit by simplifying a DRAM.
It is a further object of the present invention to reduce a test time for the DRAM and to increase the operating speed of the semiconductor integrated circuit by eliminating an overhead of a write cycle during batch write of test data to the DRAM.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.